Method for fabricating a microelectronic circuit and microelectronic circuit

ABSTRACT

A method for fabricating a microelectronic circuit having an improved electrically conductive element. The method includes providing a finished processed microelectronic circuit having a monolithically integrated coil and having a passivation layer situated above at least the monolithically integrated coil. The method further comprises removing at least part of the passivation layer above the monolithically integrated coil and applying a metal layer above the monolithically integrated coil so that the metal layer is electrically coupled to the monolithically integrated coil.

[0001] A microelectronic circuit is disclosed in [1]. Thismicroelectronic circuit is an integrated semiconductor element having anelectrically conductive element (an inductor coil).

[0002] One problem with such electrically conductive elements known fromthe prior art is that their inherent conductivity is relatively low.This requires special operating conditions, such as e.g. lowtemperatures, or, under defined operating conditions, e.g. at definedtemperatures, leads to a poor quality factor of the electricallyconductive element. This in turn leads to a poor quality factor of theintegrated semiconductor element having the conductive element.

[0003] Furthermore, [2] describes a coil applied on a ceramic substrate.

[0004] [3] describes a method for repairing a semiconductor memory. In asemiconductor chip having fuses and a redundancy memory cell which canreplace a normal memory cell, in the case where a normal memory cell isdefective, the fuses are cut out in order thereby to connect theredundancy memory cell instead of the defective normal memory cell.

[0005] [4] describes a method for fabricating an inductive element or acapacitor element on a semiconductor chip, there being arranged, in adielectric arranged between two metal layers of predetermined formparallel to the chip plane, at least one metal plug of the length of themetal layers, which metal plug effects through-plating connection of themetal layers.

[0006] [5] describes a method for fabricating a monolithicallyintegrated coil in a microelectronic circuit, in which the coil isformed during the production process of the microelectronic circuit. Apatterned dielectric layer is applied on a first electrically conductivelayer applied on a substrate and a second, patterned, electricallyconductive layer is applied on said dielectric layer. The first andsecond electrically conductive layers are electrically contact-connectedto one another through the dielectric layer.

[0007] Consequently, the invention is based on the problem of improvingthe quality factor of a monolithically integrated coil in amicroelectronic circuit.

[0008] According to the invention, this problem is solved by theprovision of a method for fabricating a microelectronic circuit havingan improved electrically conductive element.

[0009] According to the invention, a microelectronic circuit having animproved monolithically integrated coil as electrically conductiveelement is fabricated by a method

[0010] in which provision is made of a finished processedmicroelectronic circuit having a monolithically integrated coil andhaving a passivation layer situated above at least the monolithicallyintegrated coil;

[0011] in which at least a part of the passivation layer above themonolithically integrated coil is removed; and

[0012] in which a metal layer is applied above the monolithicallyintegrated coil in such a way that the metal layer is electricallycoupled to the monolithically integrated coil.

[0013] The monolithically integrated coil is fabricated fromelectrically conductive material.

[0014] The problem on which the invention is based is also solved by theprovision of a microelectronic circuit having at least onemonolithically integrated coil, fabricated according to this method, aselectrically conductive element.

[0015] The method according to the invention thickens an alreadyexisting electrically conductive, monolithically integrated coil in afinished processed microelectronic circuit with a metal which has thesame conductivity as, or a higher conductivity than, the metal of themonolithically integrated coil. By virtue of this thickening of themonolithically integrated coil, more conductive material is applied oninterconnects of the monolithically integrated coil by comparison withthe unthickened state, and this leads to a reduced impedance bycomparison with the unthickened state. The reduction of the impedance isaccompanied by a corresponding increase in the conductivity of theaffected monolithically integrated coil of the microelectronic circuit.

[0016] Consequently, the invention advantageously achieves an improvedquality factor of the electrically conductive element of amicroelectronic circuit.

[0017] A further advantage of the method according to the invention isthat the method follows the fabrication of an already finished processedmicroelectronic circuit.

[0018] The expression “finished processed” is to be understood to meanthat state of the microelectronic circuit which the microelectroniccircuit has upon entering the next higher stage of the fabricationmarket. In the context of the invention, the product is to be regardedas finished processed for example if a manufacturer of computercomponents only has to incorporate this microelectronic circuit into acomputer component without changing the nature of the microelectroniccircuit in any way, and the microelectronic circuit, and therefore alsothe computer component itself, is capable of performing the plannedfunction.

[0019] In the context of the invention, then, a finished processedmicroelectronic circuit is a circuit whose state after conventionalfabrication is completed and concluded in such a way that it couldnormally functionally fulfil the purpose envisaged for this circuit,without having to be subjected to further method steps in thefabrication process.

[0020] A further advantage of the method according to the invention isthat the thickness of the applied metal layer can be adapted as desiredto specific requirements in the context of the same method step. Thismeans that the method according to the invention achieves a high degreeof flexibility with regard to the configuration of the applied metallayer, without additional method steps being necessary.

[0021] According to one embodiment of the method according to theinvention, before the application of the metal layer, an electricallyconductive auxiliary layer may additionally be applied at least abovethe monolithically integrated coil of the microelectronic circuit, sothat the metal layer is subsequently applied on the auxiliary layer.

[0022] Depending on the thickness, configuration and nature of theelectrically conductive auxiliary layer, the latter can be used fordifferent purposes.

[0023] By way of example, in the case of poor adhesion between the metallayer and the monolithically integrated coil and/or poor adhesionbetween the metal layer and further regions of the passivation layer ofthe microelectronic circuit which have not been removed, theelectrically conductive auxiliary layer may be used to improve the saidadhesion. It is thus ensured that the metal layer adheres fixedly on thesurface at least of the monolithically integrated coil of themicroelectronic circuit.

[0024] However, the auxiliary layer may also inherently have a diffusionblocking function, thereby ensuring that metal atoms of the metal layerapplied thereon do not diffuse into the unremoved regions of thepassivation layer and thereby contaminate the latter. This barrierfunction of the auxiliary layer is of great importance for example inthe case when copper is used as metal for the metal layer. This isbecause copper atoms tend to diffuse, over a relatively long time, intosilicon dioxide, which is a material that is often used for passivationlayers. By utilizing the diffusion blocking function of the auxiliarylayer, such diffusion of the copper atoms into the passivation layer canessentially be prevented.

[0025] The auxiliary layer may be applied

[0026] to the electrically conductive elements of the microelectroniccircuit, or

[0027] to the electrically conductive elements of the microelectroniccircuit and to possibly unremoved regions of the passivation layer.

[0028] As an example of the flexibility of the method according to theinvention, regions of the metal layer and/or of the auxiliary layer canbe removed independently of one another or together by means of a wet ordry etching method. By way of example, after the removal of the at leastone part of the passivation layer above the monolithically integratedcoil, a metal layer may be applied over the whole area on themicroelectronic circuit, and this metal layer can then be etched away inplaces by means of a wet or dry etching method in such a way as toproduce the desired patterning at least above the underlyingmonolithically integrated coil. No auxiliary layer is used in this case.

[0029] For the case where an auxiliary layer is used, after the removalof the at least one part of the passivation layer above themonolithically integrated coil, the said auxiliary layer can be appliedover the whole area on the surface of the microelectronic circuit.Proceeding from this state of production, there are then, in particular,two possibilities in the context of further processing.

[0030] As a first possibility, the metal layer may be applied over thewhole area on the auxiliary layer, and the metal layer and theunderlying auxiliary layer may be removed together, i.e. in a singlemethod step, by means of a wet or dry etching method in such a way as toproduce the desired patterning of the now thickened, monolithicallyintegrated coil.

[0031] As a second possibility, after the application of the auxiliarylayer, the latter may be etched away in places to form a desiredpatterning, and the metal layer may then be applied on the alreadypatterned auxiliary layer. Afterwards, the metal layer is removed inplaces by means of a second etching method in such a way as to producethe desired structure of the metal layer. By way of example, the metallayer may be etched away in such a way that it lies only above thosepoints of the electrically conductive element which are already coveredwith a section of the auxiliary layer.

[0032] However, it is also perfectly possible that, by virtue of suchstaggering of the etching methods, i.e. by virtue of successiveimplementation of the removal of the auxiliary layer and of the metallayer, all possible layer combinations with regard to the nature and therelative positions of the layers with respect to one another arepossible for the metal layer crucial for conductivity.

[0033] Thus, the effect that can be achieved by such successiveimplementation of the etching methods for the auxiliary layer and themetal layer is that an individual microelectronic circuit is formed, sothat the metal layer for example:

[0034] lies directly on the monolithically integrated coil of themicroelectronic circuit;

[0035] lies on at least one region of the auxiliary layer whichintrinsically lies directly above a monolithically integrated coil ofthe microelectronic circuit;

[0036] lies directly on the unremoved regions of the passivation layer;or

[0037] lies on at least one region of the auxiliary layer whichintrinsically lies directly on the unremoved regions of the passivationlayer.

[0038] The above possibilities show the flexibility of the invention'smethod for fabricating a microelectronic circuit having at least onemonolithically integrated coil in which the quality factor of the saidcircuit is improved by reducing the inherent impedance of themonolithically integrated coil.

[0039] It should be noted that the removal—carried out at the beginningof the method—of regions of the passivation layer can also be effectedby means of a wet or dry etching method. Moreover, specific regions ofthe passivation layer, the metal layer and/or the auxiliary layer can beremoved in a targeted manner as explained above with the aid of knownphotolithographic methods.

[0040] The metal layer and the auxiliary layer can be applied by meansof an electrodeposition method, an electroless deposition method, avapour deposition method, a sputtering method, an electrodepositionmethod or a plasma CVD method (CVD=Chemical Vapor Deposition).

[0041] According to the invention, the metal layer is formed with athickness of 0.5 μm to 10 μm, preferably with a thickness of 3 μm to 6μm. The metal layer may be formed from a metal which corresponds to themetal of the electrically conductive element, or which is different fromthe metal of the electrically conductive element. According to theinvention, when forming the metal layer, use is made of a metal of highconductivity, e.g. a metal whose conductivity exceeds that of thematerial of the monolithically integrated coil. Examples of such metalswhich can be used in the method according to the invention are copper,gold, silver, platinum, aluminium or a plurality thereof.

[0042] The expression “a plurality thereof” is to be understood to meaneither the separate use of a plurality of metals, so that differentregions of the microelectronic circuit are coated with different metalsin each case, or the use of a plurality of metals as a homogeneous alloywhich coats the microelectronic circuit over the whole area.

[0043] It should be noted that any desired metal having a highconductivity can be used in the method according to the invention.

[0044] The auxiliary layer, if present, is preferably formed with athickness of 0.5 μm to 20 μm, more preferably with a thickness of 5 μmto 10 μm. To form the auxiliary layer it is possible to use conductivematerials, for example tungsten silicide, titanium, platinum, nickel,chromium, nickel-chromium alloy, molybdenum, palladium or rhodium.

[0045] The invention also comprises a microelectronic circuit having atleast one monolithically integrated coil which is fabricated by themethod according to the invention.

[0046] Exemplary embodiments of the invention are illustrated in thefigures and are explained in more detail below.

[0047] In figures:

[0048]FIGS. 1a to 1 d show, in a diagrammatic sectional view of afinished processed, monolithically integrated coil, the sequence of anexemplary embodiment of the method according to the invention in which ametal layer is applied directly on the interconnects of the coil;

[0049]FIGS. 2a to 2 d show, in a diagrammatic sectional view of afinished processed, monolithically integrated coil, the sequence of anexemplary embodiment of the method according to the invention in whichan auxiliary layer and a metal layer are applied on the interconnects ofthe coil, the auxiliary layer and the metal layer being etched away inthe same method step;

[0050]FIGS. 3a to 3 d show, in a diagrammatic sectional view of afinished processed, monolithically integrated coil, the sequence of anexemplary embodiment of the method according to the invention in whichan auxiliary layer and a metal layer are applied on the interconnects ofthe coil, the auxiliary layer and the metal layer being etched away inmutually separate method steps; and

[0051]FIGS. 4a to 4 c show further possible exemplary embodiments of themethod according to the invention in which the metal layer not only liesabove the interconnects of the coil but also lies with and without anintervening auxiliary layer on unremoved regions of the passivationlayer.

[0052]FIG. 1a shows a diagrammatic cross-sectional view of amicroelectronic circuit having a substrate 100, a passivation layer 101and interconnects 102 of a coil that is to be regarded as anelectrically conductive element. In the case of the finished processedmicroelectronic circuit shown in FIG. 1a, the interconnects 102 are eachcovered by a part of the passivation layer 101.

[0053]FIG. 1b shows a diagrammatic cross-sectional view of themicroelectronic circuit from FIG. 1a, in which the regions of thepassivation layer 101 above the interconnects 102 have been removed,with the result that removed regions 103 are formed above the respectiveinterconnects of the monolithically integrated coil.

[0054]FIG. 1c shows the result of a whole-area application of a metallayer 104 on the surface of the microelectronic circuit. The metal ofthe metal layer 104 expediently has an intrinsic conductivity which ishigher than the conductivity of the metal of the interconnects 102. Thismetal layer 104 makes contact both with the interconnects 102 of thecoil directly and with the unremoved regions of the passivation layer101. Furthermore, the metal layer 104 makes contact with the sidewallsof the removed regions 103 shown in FIG. 1b, which sidewalls areproduced by the removal of those regions of the passivation layer 101which are situated above the interconnects 102 of the coil.

[0055]FIG. 1d shows the result of the removal of specific regions of themetal layer 104 from FIG. 1c in such a way that the metal of the metallayer 104 remains only above the respective interconnects 102 of thecoil, in a manner such that it is in direct electrical contact with thesaid interconnects. Thus, the interconnects 102 of the coil arethickened by comparison with their initial state, which brings about anincrease in the intrinsic conductivity of the interconnects 102. Thisincreased conductivity consequently leads to an improved quality factorof the coil.

[0056] In a further step (not shown), the surface of the passivationlayer 101 and also the interconnects 102 of the coil, whichinterconnects are now thickened by the metal layer 104, are coated witha further passivation layer for protection against external effects.

[0057]FIG. 2a shows the microelectronic circuit in the production stateof FIG. 1b, in which the regions of the passivation layer 201 above therespective interconnects 202 of the coil have been removed.

[0058]FIG. 2b shows the result of the application of an auxiliary layer203 on the entire surface of the microelectronic circuit. In this case,all areas of the unremoved passivation layer 201 and also of theinterconnects 202 of the coil are coated with the auxiliary layer 203.Furthermore, areas of the passivation layer 201 to the sides of theinterconnects 202 of the coil, which areas have been uncovered by theremoval of those regions of the passivation layer 201 which are situatedabove the interconnects 202, are also covered with the auxiliary layer.

[0059] It should be noted that the illustration represented in FIG. 2cis a sectional view, i.e. the interconnects 202 extend both out from thearea of the paper and in from the rear area of the paper, with theresult that the regions uncovered by the removal of the passivationlayer 201 are elongate, trench-shaped cutouts in the surface of thepassivation layer 201. For this reason, the auxiliary layer 203 clingingtightly to these cutouts also assumes this elongate, trench-shapedconfiguration.

[0060]FIG. 2c shows the result of the application of a metal layer 204on the auxiliary layer 203.

[0061]FIG. 2d shows the result of the removal of the metal layer 204 andof the auxiliary layer 203 in such a way that only those regions of thepassivation layer 201 of the auxiliary layer 203 and of the metal layer204 which are situated above the interconnects 202 of the coil remainafter the removal process. Consequently, according to this exemplaryembodiment, the metal layer 204 is separated from the respectiveinterconnects 202 of the coil by the auxiliary layer 203. Since theauxiliary layer 203 has an electrical conductivity, as explained above,the electrical contact connection between the respective interconnects202 and the metal layer 204 is ensured.

[0062] In the case of the exemplary embodiment illustrated in FIG. 2, itshould be noted that the removal of the metal layer 204 and of theauxiliary layer 203 can be effected in a single step, e.g. by wet or dryetching.

[0063] In a further step (not shown), the surface of the passivationlayer 201 and also the interconnects 202 of the coil, whichinterconnects are now thickened by the metal layer 204, can be coatedwith a further passivation layer for protection against externaleffects.

[0064] Proceeding from FIG. 1b, FIG. 3a shows the result of theapplication of an auxiliary layer 303 over the whole area on themicroelectronic circuit. In this case, the uncovered interconnects 202of the coil and also those regions of the interconnects 202 of the coilwhich were uncovered by the initially effected removal of the parts ofthe passivation layer 301, and also those regions of the passivationlayer 301 which were not removed are coated with the auxiliary layer303.

[0065]FIG. 3b shows the production state of the microelectronic circuitafter the removal of the auxiliary layer 303 in such a way that onlythose regions of the auxiliary layer 303 which lie directly above therespective interconnects 302 of the coil remain. The auxiliary layer isetched away for example by means of a wet or dry etching method.

[0066] Afterwards, a metal layer 304 is applied over the whole area onthe microelectronic circuit. The metal layer 304 makes contact with onlythe topmost areas of the passivation layer 301 and also those regions ofthe auxiliary layer 303 which lie directly above the respectiveinterconnects 302 of the coil.

[0067]FIG. 3d shows the result of the removal of regions of the metallayer 304 in such a way that the metal layer 304 only remains abovethose regions where there is already a section of the auxiliary layer303.

[0068] It should be noted that, in the exemplary embodiment of themethod which is illustrated in FIG. 3, the removal of the auxiliarylayer 303 and of the metal layer 304 is effected in two mutuallyseparate method steps.

[0069] In a further step (not shown), the uncovered surface of thepassivation layer 301 and also the interconnects 302 of the coil, whichinterconnects are now thickened by the metal layer 304, can be coatedwith a further passivation layer for protection against externaleffects.

[0070] The exemplary embodiment shown in FIG. 4a firstly proceeds fromthe production state from FIG. 1c, in which a metal layer 104 wasapplied without an auxiliary layer over the whole area on the surface ofthe microelectronic circuit. Proceeding from FIG. 1c, the metal layer104 is then removed in such a way that regions remain both directlyabove the respective interconnects of the coil 402 and directly abovethe unremoved regions of the passivation layer 401. Consequently, e.g.any remaining regions of the area of the passivation layer 401 can beutilized for developing the already existing coil.

[0071] In a further step (not shown), the removed regions of thepassivation layer 401 and also the interconnects 402 of the coil, whichinterconnects are now thickened by the metal layer 403, can be coatedwith a further passivation layer for protection against externaleffects.

[0072]FIG. 4b proceeds from the production state from FIG. 2c, in whichboth an auxiliary layer 203 and a metal layer 204 were appliedsuccessively on the surface of the microelectronic circuit. FIG. 4bshows the result of the removal both of those regions of the metal layer403 (corresponds to the metal layer 104 in FIG. 2c) which lie directlyabove the respective interconnects 402 of the coil, and of other regionsof the metal layer 403 which lie on the auxiliary layer above theunremoved region of the passivation layer 401.

[0073]FIG. 4c shows the end result after the removal of those regions ofthe auxiliary layer 404 on which there is no metal layer 403.

[0074] It should be noted that the removal of the metal layer 403 andthe removal of the auxiliary layer 404 can be effected in two mutuallyseparate method steps or as a single method step.

[0075] In a further step (not shown), the removed regions of thepassivation layer 401 and also the interconnects 402 of the coil, whichinterconnects are now thickened by the metal layer 403, can be coatedwith a further passivation layer for protection against externaleffects.

[0076] The exemplary embodiments of the invention which are shown inFIG. 4 are to be understood as by way of example to the effect thatnumerous different configurations of the coil and generally of themicroelectronic circuit with regard to the relative arrangements of themetal and auxiliary layers are possible by separation of the removalsteps of the metal layer and of the auxiliary layer.

[0077]FIG. 5 shows a further exemplary embodiment of the invention,revealing a substrate 500, a passivation layer 501, interconnects 502 ofa coil in sectional view, a metal layer 503 and a layer of photoresist504. In FIG. 5a, firstly a layer of photoresist 504 is applied to thepassivation layer 501 and is etched photolithographically above thelocations of the passivation layer 501 which, for their part, aresituated above the interconnects 502 of the coil.

[0078]FIG. 5b shows the result after the etching of the regions of thepassivation layer 501 which are situated above the interconnects 502.

[0079] In FIG. 5c, the microelectronic circuit is then subjected to anelectrodeposition method, with the result that the metal layer 503 growsas it were “automatically” on the interconnects. The effect thusachieved is that the layer of photoresist 504 functions as a mask whichdetermines the local specificity of the metal growth.

[0080] The layer of photoresist 503 can then subsequently be removed togive the result shown in FIG. 5d. This end result corresponds to thatfrom FIG. 1d.

[0081]FIG. 6 shows a further exemplary embodiment of the invention,revealing a substrate 600, a passivation layer 601, interconnects 602 ofa coil in sectional view, an electrically conductive auxiliary layer603, a metal layer 604 and a layer of photoresist 605. FIG. 6acorresponds to the production state of FIG. 1b, in which those regionsof the passivation layer 601 which are situated above the interconnects602 of the coil have already been etched away.

[0082] In FIG. 6b, firstly a layer of photoresist 605 is applied to thepassivation layer 601 and is etched photolithographically above thelocations of an electrically conductive auxiliary layer 601 which, fortheir part, are situated above the interconnects 602 of the coil.

[0083] In FIG. 6c, the microelectronic circuit is then subjected to anelectrodeposition method, with the result that the metal layer 604 growsas it were “automatically” on the interconnects. The effect thusachieved is that the layer of photoresist 605 functions as mask whichdetermines the local specificity of the metal growth.

[0084] The layer of photoresist 605 can then subsequently be removed togive the result shown in FIG. 6d. This end result corresponds to thatfrom FIG. 2d.

[0085] The following publications are cited in this document:

[0086] [1] EP 551735

[0087] [2] U.S. Pat. No. 4,613,843

[0088] [3] DE 197 21 310 A1

[0089] [4] DE 197 37 294 A1

[0090] [5] WO 95/05678

1. Method for fabricating a microelectronic circuit having at least onemonolithically integrated coil, in which provision is made of a finishedprocessed microelectronic circuit having a monolithically integratedcoil and having a passivation layer situated above at least themonolithically integrated coil; in which at least a part of thepassivation layer above the monolithically integrated coil is removed;and in which a metal layer is applied above the monolithicallyintegrated coil in such a way that the metal layer is electricallycoupled to the monolithically integrated coil.
 2. Method according toclaim 1, in which an electrically conductive auxiliary layer is appliedat least above the monolithically integrated coil, and in which themetal layer is applied on the auxiliary layer.
 3. Method according toclaim 2, in which regions of the auxiliary layer are removed before theapplication of the metal layer in such a way that, after the removal,the auxiliary layer is situated above the monolithically integrated coilor above the monolithically integrated coil and above an unremovedregion of the passivation layer.
 4. Method according to one of claims 1to 3, in which regions of the metal layer are removed in such a way thatthe metal layer lies directly above the monolithically integrated coil.5. Method according to either of claims 2 and 3, in which regions of themetal layer are removed in such a way that the metal layer lies directlyabove the auxiliary layer.
 6. Method according to one of claims 1 to 5,in which the removal of the passivation layer and/or of the metal layeris carried out by means of a wet or dry etching method.
 7. Methodaccording to one of claims 2 to 5, in which the auxiliary layer isremoved by means of a wet or dry etching method.
 8. Method according toone of claims 1 to 7, in which the metal layer is applied by means of anelectrodeposition method, an electroless deposition method, a sputteringmethod, a vapour deposition method, an electrodeposition method, or aplasma CVD method.
 9. Method according to one of claims 2 to 7, in whichthe auxiliary layer is applied by means of one of the methods listed inclaim
 8. 10. Method according to one of claims 1 to 9, in which themetal layer is formed with a thickness of 0.5 μm to 10 μm.
 11. Methodaccording to claim 10, in which the metal layer is formed with athickness of 3 μm to 6 μm.
 12. Method according to one of claims 1 to11, in which the metal layer is formed from a metal which corresponds tothe metal of the monolithically integrated coil, or which is differentfrom the metal of the monolithically integrated coil.
 13. Methodaccording to one of claims 1 to 12, in which the metal layer is formedfrom Cu, Au, Ag, Pt, Al or a plurality thereof.
 14. Method according toone of claims 2 to 13, in which the material used for the auxiliarylayer is WSi, Ti. Pt, NiCr Mo, Pd, or Rh.
 15. Method according to one ofclaims 2 to 14, in which the auxiliary layer is formed with a thicknessof 0.5 μm to 20 μm.
 16. Microelectronic circuit, having at least onemonolithically integrated coil fabricated according to one of claims 1to 16.